I've been diving online for days looking for technical information on the Apple Macintosh 128k hardware. In truth, I didn't find much, at least what I was looking for.
I was studying the diagrams and photos of the motherboard that I found, and I understood that the "custom" chips have a crucial role in the functioning of the Mac.
They are called "PAL", or "Programmable Array Logic", and are programmed from the factory with particular programs that tell the chip how to configure the output signals based on the input signals.
They are used mostly to translate memory addresses into activation signals for specific components, this means that for example if I want to read bytes from the RAM, or from the serial port, the address of the access must stay in a specific range.
BMU0, BMU1, TSM, TSG, LAG, ASG are the names of the 6 wonders that do the hard work of communication between components and the CPU.
Let me ask ChatGPT if he knows something about them.
The document "Inside Macintosh" provides some information about the PAL (Programmable Array Logic) chips used in the Macintosh 128K, but it does not offer a detailed explanation of each specific chip (BMU0, BMU1, TSM, TSG, LAG, ASG). These chips are part of the custom hardware design of the Macintosh 128K and play crucial roles in its operation. Here's a brief overview based on general knowledge:
1. BMU0 and BMU1 (Bus Management Unit 0 and 1): These chips are likely involved in managing data transfers across different buses within the computer system, such as between the CPU, memory, and I/O devices.
3. TSG (Timing Signal Generator): Similar to the TSM, the TSG would be involved in generating timing signals necessary for the operation of different parts of the computer, such as the CPU and memory.
4. LAG (Logic Array Generator): This chip might be used for generating specific logic functions required for the operation of the computer, possibly in relation to the CPU or memory management.
5. ASG (Analog Signal Generator): The ASG is mentioned in the context of the disk interface. It reads the disk speed buffer in RAM and generates voltages that control the disk speed. This is crucial for reading, writing, formatting, and ejecting disks.
These chips, being part of the custom hardware design of the Macintosh 128K, were specifically tailored to meet the unique requirements of the system, contributing to its efficiency and performance. For more detailed information about these chips, additional technical resources or hardware manuals specific to the Macintosh 128K would be required.
So, from the manual "Inside Macintosh" not that much, so I did some research, and I have sound some more information:
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BMU1 is a 16L8 device that performs the major address decoding functions. It has as inputs the higher order address lines A21, A22, and A23 from the processor, along with the overlay bit (for a description of the overlay bit, see the August issue). These bits are decoded to generate enable signals for the RAM, ROM, IWM (disk controller), and the SCC serial chip. |
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LAG is a 16R8 device that performs the majority of the video control functions. It has as inputs most of the video address counter outputs, which are decoded to create output signals that load the video shift register, provide the CRT sweep circuitry with horizontal and vertical syncs, increment and reset the video address counters, and switch the RAM address multiplexers between CPU, video, and sound addresses. |
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BMU0 is a 16R4 device that generates RAM read and write signals from the RAM enable output of BMU1 and the processor R/W line. It is also used as a counter to create two video address lines (VA12 and VA13) because the video counter is only 12 bits wide (VA0-VA11). In addition, it also generates DTACK, the data transfer acknowledges the handshake signal to the processor and synchronizes the output of the video shift register with the master oscillator. This is a very good example of the many different types of functions that can be handled with a single programmable device. |
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TSM is a 16R4 device whose major function is control of the dynamic RAM. For inputs, it has the decoded RAM enable signal, along with the address and data strobes from the processor which signify whether the data transfer will be low byte, high byte, or word. From these, the RAS and CAS strobes are generated, and the row/column address multiplexer is controlled. Until there were PALs, this type of dynamic RAM control function required either about 10-20 discrete TTL packages or a 40-pin LSI dynamic RAM controller which usually didn't do what you wanted anyway. |
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ASG is a 16R8 device which illustrates why PALs can be so valuable. Its primary purpose is to take the 6-bit disk speed value which is fetched at the end of every horizontal retrace period and convert it to a pulse-width modulated signal. Basically, it's a 6-bit counter. This leaves a couple of inputs and outputs available, which are used to control the loading of the sound generator pulse-width modulator, which is a counter made up of TTL devices. If a discrete counter had been used for the disk PWM, another chip would have been required for the sound PWM load function. Using a PAL for a simple counter function in this instance saved a chip in the design. |
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TSG is a 16R6 device that illustrates the power of programmable logic. It serves a couple of mundane functions concerning interrupts and the keyboard clock, but by far its most interesting job is as a clock generator for the SCC serial chip. The master oscillator frequency in the Macintosh is 15.667 MHz. This is divided by 2 in the TSG to get the 7.834 MHz processor clock. In order for the SCC to be able to operate at a baud rate of 230.4 KBaud, which is what AppleTalk requires, it needs an input clock frequency of 3.686 MHz. |
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If you pull down your calculator desk accessory, you'll find that 15.667 ÷ 3.686 = 4.25. This means that the TSG needs to divide the 15.667 MHz master oscillator by 4.25 in order to get a 3.686 MHz clock. How is this done, since 4.25 is not even an integer, let alone a binary number?
Let's call the 15.667 MHz clock the MO_clk and the 3.686 MHz clock the SCC_clk. For every 17 MO_clk periods, there are 4 SCC_clk periods (17 ÷ 4 = 4.25). The way the TSG generates the SCC_clk is to count to 4 three times and then count to 5 once (4 + 4 + 4 + 5 = 17). See Figure 11 for a graphical description. Try that using a single TTL counter chip!
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